Learn to describe real hardware in text.

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Welcome — here's how this works

You don't need to know anything about hardware, and only the tiniest bit about programming (if you know what a for loop is, you're set). Everything else is built up from scratch, in order. Read a lesson, type the examples yourself, run them, then do the homework. That's the whole loop.

What Verilog actually is

Verilog is a Hardware Description Language (HDL). You use it to describe digital circuits — collections of logic gates, wires, and memory — using text. A software tool then either simulates that circuit on your computer (to check it works) or turns it into a real chip or FPGA. You're not writing a program that "runs." You're writing a blueprint for a physical thing.

Two things you can do with a design

Simulate it — run it virtually on your computer to confirm it behaves correctly. You'll do this constantly; a testbench (Lesson 6) feeds it inputs and checks its outputs. Synthesize it — convert it into actual gates on a chip or FPGA. This course focuses on writing clean designs and proving they work through simulation, which is exactly how real chip teams spend most of their time.

Set up your tools (2 minutes, nothing to install)

You need somewhere to run code. The fastest path, with zero setup:

• Go to EDA Playground (edaplayground.com) and make a free account.
• On the left, set the language/simulator to Icarus Verilog.
• Paste your design in the left pane and your testbench in the right pane, then click Run. Output appears at the bottom.

That's all you need for this entire course. (If you'd rather work on your own machine later, install the free tools Icarus Verilog to compile/simulate and GTKWave to view waveforms — but the website is the easy way to start.)

Section 0 The absolute basics · 10 min

Ground zero: bits, gates, and wires

Before any Verilog, let's build the handful of physical ideas the whole field rests on. If you've never thought about how computers work underneath, this section is for you. If you have, skim it — but the interactive gate below is worth a minute regardless.

Everything is a 1 or a 0

Inside a chip, there are no numbers, letters, or pictures — just millions of tiny wires, and each wire is either at a high voltage or a low voltage at any moment. We call high 1 and low 0. That single distinction — on or off — is a bit, the atom of all digital electronics.

Counting with only 1s and 0s: binary

With one bit you can count to 1 (it's 0 or 1). To count higher, line up more bits. This is binary — the same idea as ordinary counting, but each column is worth twice the one to its right instead of ten times.

In the everyday (decimal) number 365, the columns are worth 100, 10, 1. In binary, the columns are worth 8, 4, 2, 1 (and onward: 16, 32, 64…). To read a binary number, add up the column values wherever there's a 1:

Eight bits together make a byte, which can represent 0 through 255 — that's 256 different patterns. You'll see bytes everywhere. (Lesson 2 adds hexadecimal, a shorthand that makes long binary numbers readable. Don't worry about it yet.)

Logic gates: tiny decision-makers

So we have bits on wires. To compute, we need things that look at incoming bits and produce a new bit. Those things are logic gates. Each gate is a simple, fixed rule. The five you'll use constantly:

• AND — output is 1 only if both inputs are 1. ("I'll go if Sam and Alex come.")
• OR — output is 1 if either input is 1. ("I'm happy with tea or coffee.")
• NOT — one input, and it flips it. 1 becomes 0, 0 becomes 1. ("Whatever you said, the opposite.")
• XOR — "exclusive or": output is 1 if the inputs are different. ("One of us pays, not both.")
• NAND — AND followed by NOT: 1 unless both inputs are 1. (Quietly, this one gate can build every other gate — it's the workhorse of real chips.)

Don't memorize these. Flip the inputs below and watch what each gate does — that's how they'll actually stick.

Wires and circuits

A wire carries one bit from one place to another. Connect gates together with wires — feeding the output of one gate into the input of the next — and you have a circuit. String enough gates together and you can add numbers, compare them, store them, and eventually run an entire processor. That's the whole game: gates wired into circuits, circuits into chips.

Writing out millions of gates by hand would be impossible. That's why Verilog exists — so you can describe the circuit you want in text, and let software work out the gates.

A peek ahead: the clock

One more idea, just to plant it. Most useful circuits need a sense of time — a way to take a step, remember something, then take the next step. That timekeeper is the clock: a signal that flips 0,1,0,1,0,1 forever, millions or billions of times per second (that's what "3 GHz" means). It's the square wave ticking at the top of this page. Each time it rises from 0 to 1, the circuit takes one step. You'll meet it properly in Lesson 4 — just know the heartbeat is coming.

That's everything you need. Onward to actual Verilog.

Lesson 1 Your first module

Your first module

Every Verilog design is built from modules. A module is a self-contained block of hardware with a name and a set of ports — the wires that carry signals in and out.

The smallest useful example: a 2-to-1 multiplexer

A multiplexer (everyone says "mux") is a digital switch. It has two data inputs and passes one of them through to the output, depending on a third input called the select line. Here's the whole thing:

Let's read it line by line, in plain English:

• module … endmodule — every module begins with module <name> (...) and ends with endmodule. Everything between them describes the hardware.
• input / output — the port list declares each signal's direction. Inputs come from the outside world; outputs go back out.
• wire — exactly what it sounds like: a physical connection that carries a value. Simple inputs and outputs are wires.
• assign — a continuous assignment. It permanently wires the right-hand expression to the left-hand wire. Whenever a, b, or sel changes, y updates instantly. This is combinational logic — no clock, no memory.
• sel ? b : a — the conditional (ternary) operator. Read it as "if sel then b, else a."

Don't just read it — flip the switches and watch the mux work. The output bulb follows whichever input the select line points at.

A second example: basic gates, all at once

You can describe logic directly with operators. This module produces four different logic functions of two inputs — and crucially, all four happen simultaneously, as four independent gates:

These four operators — & (and), | (or), ^ (xor), ~ (not) — are the ones you met in Ground Zero, now in code form. Each assign is one independent gate, and they all run in parallel forever.

Lesson 2 Signals, numbers & buses

Signals, numbers, and buses

Real designs move more than one bit at a time. This lesson covers buses (multi-bit signals), how to write numbers, the difference between wire and reg, and the operators you'll reach for constantly.

Buses: signals more than one bit wide

A single wire carries one bit. To carry several bits together — say an 8-bit number — you declare a vector with a bit range:

• [7:0] means "bits 7 down to 0," so the bus is 8 bits wide. Bit 7 is the most-significant bit (MSB, the biggest place value); bit 0 is the least-significant (LSB, the ones place).
• Grab a single bit with data[0], or take a slice: data[3:0] is the lowest four bits.

Writing numbers

Verilog number literals follow the form size'base value. The little tick mark is part of the syntax. Play with the explorer below to feel how the same value looks in binary, hex, and decimal — then the literals will read naturally.

• The base letter is b (binary), h (hex), d (decimal), or o (octal).
• Size your literals whenever you can — 4'b0000 is clearer and safer than a bare 0.

wire vs. reg — the rule that trips up everyone

Both hold values, but they're used in different places. This distinction confuses every beginner, so here's the simple version:

• wire — used for continuous assignments (assign) and for connecting modules together. Think "a real wire, driven by something."
• reg — used for any signal you assign inside an always block (coming in Lessons 3 and 4). Despite the name, a reg is not automatically a hardware register — it's just the variable type Verilog requires for that style of assignment.

The operator toolbox

You've seen a few already. These are the ones you'll use most:

Two look strange at first. Concatenation joins signals into a wider bus — {a, b} puts a on the left and b on the right. Reduction operators apply one operation across every bit of a bus — ^data is the XOR of all the bits (handy for parity checks).

Worked example: a tiny ALU-style block

This combinational module computes several results from two 4-bit inputs at once, showing buses and operators working together:

Lesson 3 Combinational logic

Combinational logic — building an adder

Combinational logic is circuitry whose outputs depend only on its current inputs — no memory, no clock. The adder is the classic example, and building one teaches you assignment, hierarchy, and the case statement.

The half adder

Adding two single bits produces a sum bit and a carry bit. That's a half adder:

Why those two gates? In binary, 1 + 1 is 10 — that's sum 0, carry 1. XOR gives a 1 when the inputs differ (0+1 or 1+0), which is exactly the sum bit; AND gives a 1 only when both are 1, which is exactly when you carry. Build the four-row truth table by hand and you'll see it line up.

The full adder

To chain additions across many bits, each stage also needs a carry-in from the stage below it. A full adder adds three bits — a, b, and a carry-in — producing a sum and a carry-out:

The sum is 1 when an odd number of the three inputs are 1 (that's what triple-XOR computes). The carry-out is 1 when at least two inputs are 1.

Building hierarchy: a 4-bit ripple-carry adder

Now the payoff. To add two 4-bit numbers, chain four full adders, feeding each stage's carry-out into the next stage's carry-in — exactly how you add on paper, column by column, carrying as you go. Building a bigger module out of smaller ones is called hierarchy, and it's done by instantiating. Set the inputs below and watch the carry ripple from right to left:

Here's the structural Verilog that wires those four full adders together:

• full_adder fa0 (...) creates one copy — an instance — of the full_adder module, named fa0.
• .a(a[0]) is a named port connection — "connect this instance's port a to the wire a[0]." Named connections are clearer and far safer than relying on the order of ports.
• The internal wire [2:0] carry holds the carries passed between stages. The last stage's carry-out becomes the module's cout.

The easy way, when you don't need the structure

In everyday designs you rarely wire up individual full adders. You just write the addition and let the tool build the adder for you:

Both styles produce an adder. The structural version teaches you what's underneath; the behavioral one (a + b) is what you'll usually write.

always @(*) and the case statement

assign is great for simple expressions, but when there are several distinct cases, an always block reads better. For combinational logic, use always @(*) — the @(*) means "recompute whenever any input changes." Signals assigned inside must be declared reg.

Here's a 2-to-4 decoder: it turns a 2-bit number into a "one-hot" output where exactly one of four lines is high.

• always @(*) — the sensitivity list (*) automatically includes every signal read inside, which prevents a whole class of bugs.
• case (in) ... endcase selects one branch based on in.
• default: — always include it. It guarantees out gets a value in every possible case.

Lesson 4 Clocks & memory

Sequential logic — clocks and memory

Everything so far has been memoryless. Real systems need to remember things — a counter must know its current count. That requires sequential logic, built from flip-flops driven by a clock.

The clock

A clock is a signal that toggles between 0 and 1 at a steady rate (it's that square wave at the top of the page). Each rising edge — the instant it goes 0 → 1 — is a "tick" at which flip-flops capture new values. Between ticks, their outputs hold perfectly steady. The clock is the heartbeat that keeps the whole design in step.

always @(posedge clk): the sequential block

Sequential logic lives in an always block triggered by a clock edge. posedge means the 0-to-1 transition (negedge is the falling edge). Anything assigned inside becomes a register: it updates at the edge and holds its value until the next one.

The D flip-flop

The simplest storage element is the D flip-flop. On each clock edge it copies its input d to its output q, and holds it. The widget below is a real D flip-flop — flip d, then click Clock and watch q capture it. Notice q does not follow d until you tick the clock:

Here's the Verilog, with a reset to force a known starting value:

• rst_n is an active-low reset — it resets when the signal is 0. The _n suffix is the standard convention for "active low."
• @(posedge clk or negedge rst_n) — this flip-flop reacts to a clock edge or reset going low. That makes the reset asynchronous: it takes effect immediately, without waiting for a clock edge.

The most important rule in this course: <= vs. =

Here's why it matters. Suppose you want a 2-stage shift register: b should take a's old value, and c should take b's old value, every clock. Written with non-blocking assignments:

With <=, every right-hand side is evaluated first using the old values, then all the updates happen at once. So c gets b's old value — correct, two real stages. If you'd used = instead, b would update to a immediately, and then c would grab the new b — collapsing two stages into one. That's a genuine bug that builds the wrong hardware.

Worked example: a counter

A counter is a register that adds one to itself each clock tick. This one has a synchronous reset and a count-enable:

• always @(posedge clk) — no reset in the sensitivity list this time, so the reset is synchronous: it only takes effect on a clock edge.
• Priority logic: reset wins; otherwise, if enabled, count up. If en is 0, the count simply holds.
• Being 4 bits, it counts 0, 1, 2, …, 15, then naturally wraps back to 0.

Worked example: a shift register

A shift register slides its bits along on each clock. Feed bits into the widget below and watch them march left, one position per tick:

The concatenation {data[6:0], serial_in} drops the top bit, shifts the rest up, and places serial_in in the lowest position — exactly what you watched happen. Shift registers are everywhere: serial links, delays, and pattern generation.

Lesson 5 Finite state machines

Finite state machines

A finite state machine (FSM) is the standard way to build control logic — anything that moves through a sequence of steps and reacts to inputs. Traffic lights, communication protocols, vending machines, and instruction decoders are all FSMs. Once you can write one cleanly, you can build real controllers.

What an FSM is

An FSM has a finite set of states, and it sits in exactly one of them at a time. On each clock edge it may move to a next state, chosen from its current state and current inputs. It also produces outputs.

• Moore machine: outputs depend only on the current state. Simpler and safer — we use this style.
• Mealy machine: outputs depend on the state and the inputs. More compact but trickier. Worth knowing the term.

The recommended structure: three blocks

A clean FSM is written as three separate pieces. This keeps the clocked part, the decision logic, and the outputs from tangling together:

1. State register — one clocked always block that updates the current state each tick (uses <=).
2. Next-state logic — one combinational always block that decides where to go next (uses =).
3. Output logic — produces the outputs from the current state.

Worked example: a "101" sequence detector

This machine watches one serial input bit each clock and raises detected for a single cycle whenever it has just seen the pattern 1, 0, 1. It even handles overlaps — the 1 that ends one match can begin the next. The states track how much of the pattern has matched so far. Feed bits in below and watch it climb toward a match:

Here is the state table the machine implements, then the three-block Verilog:

• Block 1 (state register): on each clock edge the machine moves to next_state; an asynchronous reset returns it to S0. This is the only clocked block, and it uses <=.
• Block 2 (next-state logic): a combinational case on the current state. From S2 ("saw 10"), a 1 completes the pattern and jumps to S3, while a 0 starts over at S0.
• Block 3 (output logic): detected is high exactly when the state is S3. Because the output depends only on the state, this is a Moore machine.

Lesson 6 Testbenches

Testbenches — proving your design works

Designing hardware is only half the job — proving it works is the other half, and in real chip development it's where most of the effort goes. A testbench is a separate piece of Verilog that creates your design, feeds it inputs, and checks the outputs. It runs only in simulation, so it can use conveniences real hardware can't.

What's different about a testbench

• It has no ports — it's the top of the simulation, not a reusable block.
• It uses initial blocks (which run once at the start) to apply a sequence of inputs over time.
• It uses delays — #10 means "wait 10 time units." Real hardware never has # delays; they exist only for simulation.
• It uses system tasks like $display, $monitor, and $finish to print results and end the run.

The pieces you'll use: `timescale 1ns/1ps sets the time unit; reg drives the design's inputs while wire observes its outputs; #10 advances simulated time; $display(...) prints a line like printf; $monitor(...) prints automatically whenever a listed signal changes; and $finish ends the run ($dumpfile / $dumpvars record signals to a .vcd waveform you can open later).

Worked example: exhaustively testing the full adder

A full adder has only three inputs, so we can test all eight combinations and check each against the expected result:

• full_adder dut (...) — instantiate the design under test (conventionally named dut).
• {a, b, cin} = i[2:0]; — drive all three inputs at once from the loop counter, sweeping 0 to 7.
• Self-checking: the if compares the design's output to the expected sum and flags any mismatch. A testbench that checks itself is far more useful than one you have to eyeball.

Worked example: testing a clocked design

Clocked designs need a generated clock and a reset sequence. This pattern — a free-running clock plus an initial block for stimulus — is one you'll reuse constantly:

• always #5 clk = ~clk; — toggle the clock every 5 ns, a 10 ns period that runs the whole simulation.
• Hold reset long enough to cross a clock edge, then release it and let the counter run.
• $monitor(...) — print the count every time it changes, so you can watch it climb.

A reusable testbench skeleton

Most testbenches share the same shape. Keep this template handy:

Capstone Putting it all together

Capstone: a traffic-light controller

Every lesson so far built one isolated block. Real hardware work is different: you compose several blocks into a working system, then prove the whole thing behaves with a self-checking testbench. This capstone does exactly that, small enough to read in one sitting. It folds together everything you've learned — an FSM (Lesson 5), a clocked timer and a latch (Lesson 4), combinational outputs (Lesson 3), and a testbench that decides PASS or FAIL on its own (Lesson 6).

The controller cycles green → yellow → red on a timer. It also has a pedestrian button: press it, and the next red is extended to give a longer, safer crossing, with a walk signal lit the whole time. Run it, step it tick by tick, and press the button during a green to see the next red stretch:

The design

Here's the whole controller. Notice the familiar three-block FSM shape, now with a timer and a pedestrian latch woven in:

How the pieces work together:

• The state register is the same idea as the 101 detector, but it only advances when the timer hits its last tick (timer == 4'd1). Otherwise it just counts the timer down. That's how each colour stays lit for several ticks instead of one.
• When it does advance, it reloads the timer with the right duration for the colour it's entering — and for RED, it picks the extended duration if a pedestrian is waiting.
• The pedestrian latch (ped_waiting) remembers a button press that happened at any point, holding it until red arrives, then clearing. This is why a press during green still counts — the system doesn't forget it.
• The <= rule from Lesson 4 is doing quiet but crucial work here: because the RED reload reads ped_waiting with non-blocking semantics, it sees the value before the same-edge clear, so the extension applies correctly. With blocking = this would be a subtle bug.

The testbench — proving it works

And here's the verification half: a self-checking testbench that drives the clock, watches the light, and decides PASS or FAIL on its own. No eyeballing waveforms.

What this testbench actually does, in plain English: it releases reset, waits out the power-on red, then measures how long green, yellow, and red each last and confirms they match the intended 6/2/4 ticks. Throughout, it checks the safety invariant that walk is lit only during red. Then it presses the pedestrian button during a green, advances to the next red, and confirms that red is now 6 ticks instead of 4. If anything is off, errors ticks up; at the end it prints a single verdict. Running it on a real simulator gives:

Next Where to go from here

Where to go next

You can now describe combinational logic, sequential logic, state machines, and the testbenches that prove them. That's the real foundation — here's how to keep building on it.

• Drill on HDLBits. hdlbits.01xz.net auto-grades real Verilog and has a problem for every concept in this guide. It's the fastest way to turn "I read it" into "I can write it." Work straight through its sections — they mirror these lessons almost one-to-one.
• Learn SystemVerilog. It's a superset of Verilog with cleaner types (logic instead of wire/reg), much better testbench features, and assertions. Almost all modern work uses it, and everything here carries over directly.
• Build progressively harder blocks. An ALU, then a UART (serial port), then a small FIFO, then a simple processor. Each one just combines the pieces from this course in new arrangements.
• Get an FPGA board. The inexpensive ones are excellent for learning. Blinking a real LED with your own counter is a great first milestone on actual hardware — there's nothing quite like it lighting up.
• Read other people's Verilog. Open-source cores teach idioms no tutorial can. Once the basics are comfortable, reading real designs accelerates everything.

The fundamentals never change: describe hardware, keep combinational and sequential logic separate, use = and <= correctly, and verify everything with a testbench. Everything else is built on those four things. Keep building.

Appendix A Plain-English glossary

Glossary

Every term this guide uses, defined in ordinary language. Skim it now, or come back whenever a word stops making sense.

Appendix B Quick reference

Verilog cheat sheet

The patterns you'll reach for most, in one place. Bookmark this section.

Appendix C Homework solutions

Homework solutions

Worked answers to the core problems. The point is the struggle, not the answer — so give each one a real attempt before opening these. Every module here compiles and elaborates cleanly.

Lesson 1 — first modules›

(Homework 2 — a mux that selects a when sel is 1 — is just assign y = sel ? a : b;: the two branches swapped.)

Lesson 2 — numbers & buses›

Lesson 3 — combinational logic›

Lesson 4 — sequential logic›

Lesson 5 — state machines›

Traffic-light controller (Moore — the light is just the current state). It's named traffic_light_3state so it won't clash with the capstone's traffic_light; the two pick different state encodings, which is normal — each design uses whatever is convenient:

Vending machine. Here dispense depends on the incoming coin, which makes it a Mealy-style output — natural for reacting on the same cycle a coin arrives:

Lesson 6 — testbenches›

Self-checking counter testbench with a PASS/FAIL summary:

That's the whole loop in miniature: design a block, write a self-checking testbench, run it, and trust the PASS. Keep building from here.